The field of the invention is positron emission tomography (PET) scanners and other similar medical imaging systems, and particularly the event locator circuits or other circuits of PET scanners that are employed to determine the exact times at which photons are detected during PET scans.
Positrons are positively charged electrons which are emitted by radionuclides that have been prepared using a cyclotron or other device. These are employed as radioactive tracers called xe2x80x9cradiopharmaceuticalsxe2x80x9d by incorporating them into substances, such as glucose or carbon dioxide. The radiopharmaceuticals are injected in the patient and become involved in such processes as blood flow, fatty acid, glucose metabolism, and protein synthesis. As the radionuclides decay, they emit positrons. The positrons travel a very short distance before they encounter an electron, and when this occurs, they are annihilated and converted into two photons, or gamma rays. This annihilation is characterized by two features which are pertinent to PET scannersxe2x80x94each gamma ray has an energy of 511 keV and the two gamma rays are directed in nearly opposite directions. An image is created by determining the number of such annihilations at each location within the field of view.
A typical PET scanner is cylindrical and includes a detector ring assembly composed of rings of detectors which encircle the patient and which convert the energy of each 511 keV photon into a flash of light that is sensed by a photomultiplier tube (PMT). Coincidence detection circuits connect to the detectors and record only those photons which are detected simultaneously by detectors located on opposite sides of the patient. The number of such simultaneous events (coincidence events) indicates the number of positron annihilations that occurred along a line joining the two opposing detectors. During an acquisition, coincidence events are recorded to indicate the number of annihilations along lines joining pairs of detectors in the detector ring. These numbers are employed to reconstruct an image using well-known computed tomography techniques.
In order to accurately determine coincidence events and thereby obtain useful information for producing images, PET scanners require timing circuits that accurately identify and log the exact times at which photons are received at the detectors of the scanners. These circuits, which are often referred to as event locator circuits, typically include digital counters that count time periods based upon a digital clock, and digital counter latches that receive both the count signals from the counters and impulse signals from the detectors of the PET scanner whenever photons are detected. Based upon the count signals, the counter latches effectively time-stamp the impulse signals with times indicative of when the impulse signals are received, and output this information for use by the PET scanner in determining coincidence events.
As shown in FIG. 1 (Prior Art), a timing circuit 10 for use in a conventional event locator circuit of a PET scanner includes a delay-line based counter 12 and an asynchronous counter latch 36. The delay-line based counter 12 operates by providing a clock signal 14 from a clock 16 to a binary counter 18 and then to a series of analog delay lines 20, 22 and 24. The binary counter 18, which is shown to be a 5-bit counter, counts the clock pulses from the clock 16 and outputs a 5-bit binary count signal 28. A lowest bit 26 of the binary count signal 28 alternates at the frequency of the clock signal 14, which in FIG. 1 is shown to be a 40 MHz clock having a period of 25 nsec. The binary counter 18 is chosen to be a 5-bit counter in order to allow different times to be distinguished within up to 32 cycles of the clock signal 14.
In order to measure time gradations at an even higher frequency than that of the clock signal 14, the lowest bit 26 of the binary count signal 18 is additionally provided successively to the series of analog delay lines 20-24, which in turn respectively output count signals 30, 32 and 34. The count signals 30, 32 and 34 each take on the same values as the lowest bit 26 of the binary count signal 28, except insofar as each respective count signal takes on the value of the lowest bit only after the passage of respective time delays. In the embodiment shown, in which there are three analog delay lines 20-24, each delay line delays transmission of the lowest bit 26 of the binary count signal 28 by one quarter of the period of the clock, or about 2.5 nsec. Together with the lowest bit 26 of the binary count signal 28, the count signals 30-34 output by the three analog delay lines 20-24 act as a four-bit Johnson-type counter in which the allowable states of the lowest bit of the binary count signal and the three count signals 30-34 are limited to 1000, 1100, 1110, 1111, 0111, 0011, 0001 and 0000. Therefore, by virtue of the analog delay lines 20-24, three additional state changes occur in between each change in the lowest bit 26, such that time intervals are measured at four times the clock frequency, or 100 MHz. The binary count signal 28, together with the other count signals 30-34, form an overall 8-bit count signal 54.
The asynchronous counter latch 36 includes four output registers 38, 40, 42 and 44 that respectively receive the binary count signal 28 and the three additional count signals 30-34 from the binary counter 18 and the analog delay lines 20-24. In particular, the first output register 38 is a 5-bit register capable of storing all 5 bits of the binary count signal 28, while the other output registers 40-44 are single-bit registers capable of storing the individual bits of information of the respective single-bit count signals 30-34. The four output registers 38-44, which are typically D-type flip-flops, further receive and are clocked by an event detection signal 39 that is typically a digital signal provided from one of the acquisition circuits of the PET scanner. The event detection signal 39 typically switches temporarily from a low-level to a high-level whenever photons are received at one or more detectors associated with the particular acquisition circuit. Whenever the output registers 38-44 are clocked by a rising edge of the event detection signal 39, the current values of the binary count signal 28 and the counts signals 30-34 are stored in the respective registers and also output by the registers as respective output signals 45, 46, 47, and 48. Together, the output signals 45-48 form an overall 8-bit output signal 49 that represents the times at which the event detection signal 39 switches and thus the times at which photons are received at the associated detectors of the PET scanner.
Referring additionally to FIG. 2 (Prior Art), a timing diagram 50 shows exemplary operation of the timing circuit 10 of FIG. 1. In particular, the clock signal 14 is shown to vary at a particular frequency, and this is the frequency at which the lowest bit 26 of the 5-bit binary count signal 28 is shown to vary. Additionally, the values of the respective count signals 30, 32 and 34 are shown to follow that of the lowest bit 26 of the binary count signal 28 except insofar as each successive count signal is delayed with respect to the lowest bit by successive 90 degree phase intervals due to the analog delay lines 20, 22 and 24. For example, during a period 52 of the clock signal 14 in which the binary count signal 28 has a value of 00001, the count signal 30 only takes on a high-level value (e.g., a value of 1) one-quarter of the period of the clock signal 14 after the time at which the lowest bit 26 has already taken on a value of 1. Given such operation of the delay-line based counter 12, the overall 8-bit count signal 54 based upon the binary count signal 28 and the count signals 30-34 is determined.
With this progression of the overall 8-bit count signal 54 and the operation of the asynchronous counter latch 36 as explained above, a rising edge in the event detection signal 39 at a time 66 as shown in FIG. 2 should produce the 8-bit output signal 49 also shown in FIG. 2. This is because, when the event detection signal 39 switches from a low-level to a high-level at the time 66, each of the registers 38-44 are clocked and consequently the output signals 45-48 take on the values of the binary count signal 28 and the other count signals 30-34 that currently exist at that time, namely, 00011111.
Although the timing circuit of FIG. 1 has worked well in many PET scanners, the timing circuit may no longer be effective in future PET scanners that require greater timing resolutions (e.g., timing resolutions of better than 1.5 nsec), for several reasons. To begin, analog delay lines have poor temperature and aging characteristics that can lead to inaccuracies in the time delays provided by the delay lines and consequently inaccuracies in the times ascribed to detected events. In higher-resolution machines, the negative impact of such inaccuracies becomes pronounced. Additionally, analog delay lines require physically large packaging schemes and large amounts of circuit board area (often in the range of 100 sq/mm), and also dissipate relatively large amounts of power relative to integrated circuits. As a result, use of the analog delay lines tends to complicate the design and manufacture of event locator circuits, and consequently increase the manufacturing and design costs for those circuits.
A further problem that arises from the use of timing circuits such as that shown in FIG. 1 relates to metastability of the output registers 38-44. More specifically, because the count signals 28-34 are asynchronously clocked into the output registers 38-44 by the event detection signal 39, the proper count values may not be stored and output by the registers. For example, as shown in FIG. 3 (Prior Art), prior to the switching of each count signal 28, 30, 32 and 34, there is a period of time 58, 60, 62 and 64, respectively, at which the respective output registers 38, 40, 42 and 44 are metastable. Consequently, if the event detection signal 39 happens to switch from a low level to a high level at a time 68 during one of the metastable periods 58 corresponding to the first (5-bit) output register 38, the 5-bit count value that will be stored by the register and provided as the output signal 45 is unpredictable and can take on any one of eight values 00000, 00001, 00010, 00011, 00100, 00101, 00110, and 00111. As a result, the 8-bit output signal 49 can take on eight different values 70 as shown. This is in contrast to FIG. 1, where the rising edge of the event detection signal 39 occurs at the time 66 that does not coincide with any of the metastable periods 58-64, and consequently the 8-bit output signal 49 takes on the appropriate count value.
Further referring to FIG. 3, in the example that is shown, only three of the bits 72 of the 8-bit output signal 49 can take on inappropriate values due to the effects of metastability. This is because the rising edge of the event detection signal 39 occurs during the metastable period 58 just prior to switching of the binary count signal 28 from a count of 00011 to a count of 00100, in which the lowest three bits of the binary count signal are switched. Others of the metastable periods 58 precede changes in the binary count signal 28 that involve different bits than the three lowest bits, and/or involve a different number of bits. Consequently, rising edges in the event detection signal 39 that occur during these other metastable periods 58 can cause different errors in the 8-bit output signal 49.
Further, if the rising edge of the event detection signal 39 occurs during any of the metastable periods 60, 62 and 64, only a single bit error can be produced within the 8-bit output signal 49, since each of these metastable periods precedes a single-bit change in one of the count signals 30-34. Although involving only a single bit, such an error often is unacceptable with respect to the count signals 30-34 because it can produce a value of the overall 8-bit output signal 49 that is undefined (e.g., 000101 01 would be unacceptable since the lowest three bits are not ever supposed to take on the value 101). 
These effects of metastability in timing circuits, although tolerable for many conventional PET scanners, become more problematic as timing resolutions are increased. This is particularly the case insofar as the lengths of the metastable periods for registers are not decreasing as rapidly as the frequency of operation of the clocks of the timing circuits (and overall rapidity of operation of the PET scanners) is increasing.
It would therefore be advantageous if a system and method for ascribing times to events that are detected in medical imaging systems such as PET scanners were developed that could measure and count small time gradations (e.g., time gradations of less than 1.5 nsec) by way of a technology that was more accurate, less consumptive of power, physically smaller, and less costly than analog delay lines. It would further be advantageous if such a system and method for ascribing times to detected events could limit the errors introduced as a result of metastability. In particular, it would be advantageous if, in such a system and method, ascribed times differed from the correct times by no more than one of the smallest-level time gradations measured by the system. It would additionally be advantageous if, in the case where such a system and method employed a counting system in which the count did not pass through all possible numeric states, the system and method would avoid the introduction of errors in which the count would take on undefined numeric states.
It has been discovered that a timing circuit of a medical imaging system such as a PET scanner can employ a quadrature clock using a phase locked loop circuit and two inverters in order to effectively provide a clock signal that is four times that of the actual frequency of operation of the phase locked loop circuit. The phase locked loop circuit specifically provides a first pair of clock signals that share the same frequency but are shifted in phase 90 degrees relative to one another. An additional pair of clock signals that respectively are inverted versions of the first two clock signals are produced by way of the two inverters. Thus, four clock signals are produced that share the same frequency but are shifted in phase 90 degrees relative to one another, and so effectively a clock of four times the actual clock frequency is generated, without use of analog delay lines.
Additionally, it has been discovered that it is possible to mitigate the generation of errors in the times ascribed to detected events due to the metastability of output registers of the timing circuits, by employing a status detection circuit to process an event detection signal prior to providing the information of the event detection signal to the output registers, and then synchronously (with computer signals) providing the information to the output registers. In one embodiment that operates in conjunction with the quadrature clock discussed above, the status detection circuit is a quadrature edge detection circuit with four shift registers that are respectively, separately clocked by the four clock signals of the quadrature clock. Additional respective sets of digital circuit elements coupled to the respective shift registers respectively provide edge detection signals to the respective output registers that allow updating in the overall output count only when a rising edge in the event detection signal has occurred. Because each shift register is clocked by its respective clock signal at different times than are the other shift registers, any given rising edge of the event detection signal can only occur during the metastable period of one of the shift registers. Therefore, because each shift register controls the output activity of only the respective output register to which it is coupled, the occurrence of a rising edge during a metastable period of one of the shift registers will only introduce, at most, errors in the portion of the overall output signal that is produced by the output register corresponding to that shift register.
In particular, the present invention relates to a timing circuit for use in a medical imaging system. The timing circuit includes a clock, a counter, a status detection circuit, and an output circuit. The clock has a primary frequency of operation, and the clock provides at least a first clock signal that varies at the primary frequency. The counter includes first and second counter elements coupled to the clock. The first counter element receives the first clock signal and in response provides a first count signal that varies at the primary frequency. The second counter element receives a second clock signal, and in response provides a second count signal. The status detection circuit includes first and second status circuits coupled to the clock. The first status circuit receives the first clock signal and an event detection signal and in response provides a first status signal indicative of whether the event detection signal has experienced a first status change. The second status circuit receives the second clock signal and the event detection signal and in response provides a second status signal indicative of whether the event detection signal has experienced the first status change. The output circuit includes first and second registers coupled to the clock and respectively coupled to the first and second counters and to the first and second status circuits. The first and second registers respectively receive the first and second clock signals, the first and second count signals, and the first and second status signals, respectively, and in response respectively provide first and second output signals that collectively form an overall output signal indicative of a time at which the event detection signal experienced the first status change.
The present invention further relates to a PET scanner that includes a plurality of detectors supported by a gantry, a plurality of acquisition circuits coupled to the detectors, and a plurality of event locator circuits. The acquisition circuits provide event detection signals that are related to signals received from detectors indicating that photons have been detected, and the plurality of event locator circuits receive the event detection signals. Each event locator circuit includes a respective quadrature clock and a respective quadrature counter coupled to the respective quadrature clock. Each event locator circuit additionally includes a respective quadrature edge detection circuit coupled to the respective quadrature clock and further coupled to at least one of the acquisition circuits to receive a respective one of the event detection signals. Each event locator circuit further includes a respective quadrature count latch circuit coupled to the respective quadrature clock, the respective quadrature counter and the respective quadrature edge detector. The respective quadrature count latch circuit provides a respective output signal indicative of times at which the respective event detection signal undergoes transitions of a particular type. The respective quadrature edge detection circuit prevents the respective output signal from at least one of attaining values that are undefined and attaining values that are indicative of incorrect times that are more than one clock cycle in error relative to the times at which the respective event detection signal undergoes the transitions.
The present invention further relates to a timing circuit for implementation in a medical imaging device. The timing circuit includes a phase locked loop circuit employed to generate at least two clock signals having the same frequency and each having a different phase relative to one another. The timing circuit additionally includes a means for providing a count signal based upon the at least two clock signals; and a means for associating and outputting a particular count of the count signal with a status change of an event detection signal, where the particular count is indicative of a time at which the status change occurred.
The present invention additionally relates to a method of ascribing times to events in a medical imaging system. The method includes generating a plurality of clock signals at a phase locked loop circuit, where all of the clock signals have the same frequency but have different phases, and providing each clock signal to a respective counter element. The method further includes generating at each counter element a respective count signal, where the count signals together represent successive time increments, and where the time increments are smaller than a period of the clock signals. The method additionally includes providing an event detection signal and the plurality of clock signals to a plurality of status circuits, where each clock signal is provided to a respective status circuit. The method also includes determining at each status circuit, at times at which the respective clock signals change in their states, whether the event detection signal has undergone a particular status change. The method further includes generating at each status circuit a respective status signal, where each respective status signal attains a particular level whenever the respective status circuit determines that the event detection signal has undergone the particular status change. The method additionally includes receiving at respective storage elements the respective clock signals, status signals and count signals. The method further includes storing values of the respective count signals in the respective storage elements at times when respective clock signals change in their states and when the respective status signals have attained the particular level, and outputting the stored values, as an overall output signal that indicates times at which the event detection signal has undergone the particular status change.